Traditionally, circuit boards have been tested via a bed-of-nails test fixture to detect faults, such as a failed connection between a node (i.e., a pin) of one component (e.g., an integrated circuit) on the board and a node of another component on the same board. As the density of components on a circuit board has increased, testing via the traditional bed-of-nails fixture has become increasingly more difficult to perform because of a reduced access to the nodes of the components on the board. For this reason, many circuit boards are now being designed with a Boundary-Scan test architecture of the type set forth in the ANSI/IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, incorporated by reference herein.
In accordance with the ANSI/IEEE Boundary-Scan architecture, selected components on the board are each provided with one or more Boundary-Scan cells, each comprising a single-bit register. Each Boundary-Scan cell is coupled to a node of a component, such as an input, output, input/output or control node. The Boundary-Scan cells are serially coupled in a single chain, usually referred to as a Boundary-Scan chain. To accomplish Boundary-Scan testing of a board, a string of bits is shifted through the chain of Boundary-Scan cells so that each bit is latched in a separate cell in the chain. As the bits are shifted through the chain of Boundary-Scan cells, each cell coupled to an output node of a component is "updated," i.e., the bit shifted into the cell appears at the corresponding output node coupled to it. In turn, the bit appearing at an output node will be "captured" by a Boundary-Scan cell associated with an input node of a component driven by this output node. To check whether the connections between the Boundary-Scan-testable components are fault-free, the bits in the chain of Boundary-Scan cells are shifted out and compared to a bit string obtained under fault-free conditions.
Boundary-Scan testing in the manner described above is controlled by way of a Boundary-Scan Master (BSM) on each circuit board. The BSM is comprised of a logic block that receives test information from a test and diagnosis host (i.e., a processor). In response to a test command from a host test and diagnosis processor specific to the type of circuit board to be tested, the BSM on that board accomplishes Boundary-Scan testing of the components that are coupled in the Boundary-Scan chain. In addition, the BSM may also initiate Built-In Self-Testing (BIST) of those components on the circuit board having such a capability. Further, the BSM may also be provided with the capability of compressing responses generated by the Boundary-Scan-testable components upon the completion of testing.
In theory, each BSM affords its associated circuit board an ability to accomplish nearly complete self-testing that can be exploited during testing of a system containing multiple boards. Yet there are practical limitations that have heretofore adversely affected the ability to accomplish optimal Boundary-Scan testing on a system level. For example, different systems tend to utilize different types of test and diagnosis processors, thus giving rise to different processor architectures for which account must be taken. Different protocols may also exist which adds to the issue of variability.
Further, tests performed at the system level are primarily functional tests and, as such, are generally independent of changes or revisions to the boards themselves. By contrast, Boundary-Scan and Built-In Self-Test techniques generally accomplish structural testing that may be affected by changes in the components on the board and/or the interconnections between them. Heretofore, it has been necessary to modify the system test and diagnosis software to take account of such changes, even if they do not affect the system functionality.
Thus, there is a need for a Boundary-Scan-based test and diagnosis technique that is simple and affords early fault detection with a high degree of accuracy.